Course abstract
This course is about the automatic generation of digital circuits from high-level descriptions. Modern electronic systems are specified in Hardware Description Languages and are converted automatically into digital circuits. We will introduce the VHDL Hardware Description Language, and follow it up with a discussion of the basics of synthesis topics including High-level Synthesis, FSM Synthesis, Retiming, and Logic Synthesis.
Course Instructor
Prof. Preeti Ranjan Panda
Preeti Ranjan Panda received his B. Tech. degree in Computer Science and Engineering from the Indian Institute of Technology Madras and his M. S. and Ph.D. degrees in Information and Computer Science from the University of California at Irvine. He is currently a Professor in the Department of Computer Science and Engineering at the Indian Institute of Technology Delhi. He has previously worked at Texas Instruments, Bangalore, India, and the Advanced Technology Group at Synopsys Inc., Mountain View, USA, and has been a visiting scholar at Stanford University.
Teaching Assistant(s)
Course Duration : Jan-Apr 2018
View Course
Syllabus
Enrollment : 20-Nov-2017 to 22-Jan-2018
Exam registration : 08-Jan-2018 to 07-Mar-2018
Exam Date : 28-Apr-2018, 29-Apr-2018
Enrolled
1043
Registered
35
Certificate Eligible
20
Certified Category Count
Gold
0
Elite
10
Successfully completed
10
Participation
4
Success
.jpg)
Category : Successfully Completed
Elite
.jpg)
Category : Elite
Gold
.jpg)
Category : Gold
Legend
>=90 - Elite + Gold
60-89 - Elite
40-59 - Successfully Completed
<40 - No Certificate
Final Score Calculation Logic
- Assignment Score = Average of best 6 out of 8 assignments.
- Final Score(Score on Certificate)= 75% of Exam Score + 25% of Assignment Score
Enrollment Statistics
Total Enrollment: 1043
Registration Statistics
Total Registration : 35
Assignment Statistics
Exam score
Final score